SemiEngineering
10 stories
SemiEngineeringSiliconComparing A7 CFET and A10 Nanosheet FETs From Parasitics to Chip Reliability (TUM, UNIMORE, Applied Materials) Researchers at the TU Munich, University of Modena and Reggio Emilia, and Applied Materials published a technical paper titled “System-Technology Co-Evaluation of A7 CFET and A10 NSFET Technologies…
SemiEngineeringSiliconChip Industry Week In Review AI moves deeper into chip design Cadence released a new agent for spec-to-RTL generation and early PPA optimization as part of its ChipStack AI Super Agent, reporting about 24% lower area and 18%…
SemiEngineeringSiliconA Network-on-Chip (NoC) For Multi-Die Devices The semiconductor industry is rapidly transitioning from monolithic SoCs to chiplet-based architectures.
SemiEngineeringSiliconManaging 3D-IC Design And IP By Keith Felton and Todd Burkholder The trend towards multi-chiplet heterogeneous integration is here to stay.
SemiEngineeringSiliconWhen AI Agents Cross Chip Design Silos Key Takeaways: Chip design is moving toward specialized AI agents working together. Orchestration, integration, and guardrails are becoming critical.
SemiEngineeringSiliconEDA’s Future Is Evidence-Driven Automation Key Takeaways : AI’s biggest EDA opportunity is workflow-level orchestration that coordinates tools, people, constraints, and domain knowledge across traditionally fragmented design stages, rather…
SemiEngineeringSiliconAI-Driven Device Modeling For Next Generation Quantum Applications Key takeaways: Accelerate quantum system design by rapidly developing accurate device models for circuit-level simulation.
SemiEngineeringSiliconAutonomy Levels For Design Agents: L1 To L5 Explained Agentic AI plays an important role in chip and system design, but not every “ agentic ” capability has the same degree of autonomy. In practice, autonomy is not binary.
SemiEngineeringSilicon3D Chips Push EDA Into New Territory Key Takeaways : EDA tools are helping design 3D-ICs and multi-die systems by co-optimizing across domains and speeding up design exploration.
SemiEngineeringSiliconFive Signals From The 2026 Functional Verification Study The forthcoming 2026 Siemens EDA and Wilson Research Group Functional Verification Study indicates that the IC verification problem is changing in nature, not simply growing in complexity.
Nothing matches this filter yet.