The name is the button.

An agent writes the code now, and a human thumb hovers over Accept all a hundred times a day. The honest question of this decade is what, exactly, you just accepted. So I read the diff.

Eight years as a backend engineer in Stockholm, back in Tokyo since 2023, and I still ship something small most nights, usually badly. My one rule: the only real review of a model is the thing you built with it. That is why there is no leaderboard on this site.

Around a hundred and forty sources come through — the labs' own posts, the papers, the tools, the runtimes and languages nobody is watching yet, the chip under the demo, and the newsletters people actually forward. What is moving gets counted so the week reads at a glance, and every few days I explain one mechanism in plain words.

A story here is a headline, a short excerpt, one image and the link to whoever wrote it. We never reproduce the post; the images belong to their authors. A post written in Japanese appears in Japanese, exactly as it was published, and the link goes to the original.

— Yuki Halvorsen, Tokyo

← Accept All Archive

SiliconANGLEValley

ScaleFlux puts controller chips at the heart of AI data pipeline efficiency

October 15

AI data centers have spent heavily on faster accelerators, denser racks and liquid cooling to keep that hardware running.

Chips & compute

Read at SiliconANGLE ↗

One letter a week, starting soon.

Latest

ScaleFlux puts controller chips at the heart of AI data pipeline efficiency

Related

ValleyOpen specs could cut AI data center hardware integration from a year to months SiliconANGLE

ValleyRicursive Intelligence is betting on AI-designed chips to help solve the compute crisis TechCrunch AI

ToolsVercel Connect now supports Secure Compute Vercel Blog

SiliconCharacterization of HBM Power Consumption (ETH Zurich, NYU) SemiEngineering

VoicesLab-in-the-Loop at Compute Speed — Ian Quigley, Leash Bio Latent Space

SiliconFramework Computers Triples Their Financial Support To CachyOS Phoronix