Chips and Cheese
20 stories
Chips and CheeseSiliconNvidia Vera’s System Architecture: Pushing Bandwidth Nvidia’s Vera server chip aims for high per-core performance. Its Olympus cores have massive out-of-order structures and use high per-clock throughput to meet that goal within a high core count…
Chips and CheeseSiliconNVIDIA’s Olympus Core: Pushing Server Single Threaded Performance Boundaries Server chips traditionally offered less single threaded performance than contemporary client parts. Higher core counts translate to less power per core, and the complex interconnect required to…
Chips and CheeseSiliconQualcomm’s System Level Architecture in the Snapdragon X2 Elite Laptop chips have gotten very powerful in recent years, with increasing CPU core counts, more powerful iGPUs, and higher DRAM bandwidth to feed that compute.
Chips and CheeseSiliconQualcomm’s Adreno X2 GPU Integrated GPUs have become a crucial component in recent laptop chips, thanks to a push for better graphics performance in ultraportable devices.
Chips and CheeseSiliconOn Binary Translation and its Consequences The PC market is one of the toughest areas for a CPU designer to compete in. Consumers in the PC segment expect high performance across a wide range of applications, and famously expect their devices…
Chips and CheeseSiliconArm’s C2-Ultra, G2-Ultra NX, and CSS N4 IP Editor’s Note (9/8/2026): Arm has reached out to clarify that the maximum IPC increase of the C2-Ultra core over the C1-Ultra core using the parameters shown in the endnotes is 7% along with the…
Chips and CheeseSiliconHot Chips 2026: Interviewing IBM's Christian Zoellin & Christian Jacobi Hello you fine Internet folks, Today we're at Hot Chips 2026! We join IBM to talk about their just revealed Dual-ISA z/ architecture + ARM design with Christian Zoellin, the Core Design Team Leader…
Chips and CheeseSiliconHot Chips 2026: XCENA and Samsung’s Near-Memory Compute CXL Device Memory expansion has been attractive for years, and is more relevant than ever because ML models have an insatiable appetite for memory capacity.
Chips and CheeseSiliconHot Chips 2026: Samsung’s Processing-in-Memory (PIM) In-memory compute has been an attractive proposition for many years because compute within a memory chip can exploit its higher internal bandwidth.
Chips and CheeseSiliconHot Chips 2026: Intel’s Crescent Island Hello you fine Internet folks, At Hot Chips, Intel talked a bit more about their upcoming Datacenter GPU codenamed Crescent Island.
Chips and CheeseSiliconHot Chips 2026: Fujitsu’s Monaka CPU Fujitsu’s A64FX was a pivotal core. For the Arm ecosystem, it introduced SVE. SVE continues to define Arm’s vector execution strategy to this day, with newer extensions like SME adopting a similar…
Chips and CheeseSiliconHot Chips 2026: Intel’s Diamond Rapids Hello you fine Internet folks, Intel unveiled their upcoming Diamond Rapids Server CPU at Computex where they said that Diamond Rapids has twice the memory bandwidth, PCIe Gen 6, and 50% more cores…
Chips and CheeseSiliconSiFive’s First Server Platform Hello you fine Internet folks, The RISC-V ecosystem is an ever-evolving one especially in the high-performance application class silicon space.
Chips and CheeseSiliconHot Chips 2026: Intel’s Wildcat Lake Intel’s Core Ultra series has done well with improving battery life and performance in mobile products.
Chips and CheeseSiliconHot Chips 2026: CUDA Targets RISC-V CUDA is a giant for GPU compute, which includes machine learning applications. So far, CUDA supports x86-64 and aarch64 CPUs. Now, Nvidia is looking at extending CUDA support to RISC-V.
Chips and CheeseSiliconHot Chips 2026: Applying High Bandwidth Flash (HBF) HBF, or High Bandwidth Flash, uses the same flash memory technology we see in SSDs today. Unlike SSDs, HBF is implemented much like HBM (High Bandwidth Memory).
Chips and CheeseSiliconHot Chips 2026: Samsung and HBM Base Die Opportunities HBM, or High Bandwidth Memory, stacks multiple DRAM dies on top of a base die. The dies interface with each other via TSVs, while the base die talks with whatever compute die is using the memory via…
Chips and CheeseSiliconTalking with Synopsys about the Physics of Chip Design at DAC 2026 Hello you fine Internet folks, I did an audio interview with Ravi Subramanian from Synopsys where we talked about the physics that goes into chip design and EDA tools.
Chips and CheeseSiliconNVIDIA’s Vera Whitepaper Has a Thread Loose Hello you fine Internet folks, NVIDIA has published a 45-page whitepaper explaining Vera , its first server CPU built around the company’s own Olympus core.
Chips and CheeseSiliconArm’s Cortex A55 Arm’s 5-series cores are meant for tasks where performance barely matters, but power and area efficiency are top priorities.
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