The name is the button.

An agent writes the code now, and a human thumb hovers over Accept all a hundred times a day. The honest question of this decade is what, exactly, you just accepted. So I read the diff.

Eight years as a backend engineer in Stockholm, back in Tokyo since 2023, and I still ship something small most nights, usually badly. My one rule: the only real review of a model is the thing you built with it. That is why there is no leaderboard on this site.

Around a hundred and forty sources come through — the labs' own posts, the papers, the tools, the runtimes and languages nobody is watching yet, the chip under the demo, and the newsletters people actually forward. What is moving gets counted so the week reads at a glance, and every few days I explain one mechanism in plain words.

A story here is a headline, a short excerpt, one image and the link to whoever wrote it. We never reproduce the post; the images belong to their authors. A post written in Japanese appears in Japanese, exactly as it was published, and the link goes to the original.

— Yuki Halvorsen, Tokyo

← Accept All Archive

SemiEngineeringSilicon

A Network-on-Chip (NoC) For Multi-Die Devices

September 24

Transporting the native packetized traffic of the NoC directly across die boundaries using a stable, invariant interface.

Chips & compute Blogs - SLD NoC NoC System-Level Design Arteris

Read at SemiEngineering ↗

One letter a week, in your inbox.

Latest

A Network-on-Chip (NoC) For Multi-Die Devices

Related

SiliconManaging 3D-IC Design And IP SemiEngineering

SiliconWhen AI Agents Cross Chip Design Silos SemiEngineering

Silicon3D Chips Push EDA Into New Territory SemiEngineering

AsiaSenseTime Ships SenseNova U1 Pro Image Model With Up to 8K Output via Raccoon and API Pandaily

ToolsHitting a billion tokens per minute on one GPU by combining a query planner and an inference engine Modal

GitHubQ.ANT gives away the software for its light-powered AI chips in a CUDA-style bet on developers The New Stack