The name is the button.

An agent writes the code now, and a human thumb hovers over Accept all a hundred times a day. The honest question of this decade is what, exactly, you just accepted. So I read the diff.

Eight years as a backend engineer in Stockholm, back in Tokyo since 2023, and I still ship something small most nights, usually badly. My one rule: the only real review of a model is the thing you built with it. That is why there is no leaderboard on this site.

Around two hundred sources come through — the labs' own posts, the papers, the tools, the runtimes and languages nobody is watching yet, the chip under the demo, and the newsletters people actually forward. What is moving gets counted so the week reads at a glance, and every few days I explain one mechanism in plain words.

A story here is a headline, a short excerpt, one image and the link to whoever wrote it. We never reproduce the post; the images belong to their authors. A post written in Japanese appears in Japanese, exactly as it was published, and the link goes to the original.

— Yuki Halvorsen, Tokyo

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Tom's HardwareSilicon

AMD’s Venice-X maxes out family at 5.3 GHz, returning 3D V-Cache to data center after four years

11.11

AMD missed out on deploying Turin-X CPUs in the previous generation, giving its 3D V-Cache tech a four-year hiatus from the data center following the launch of Genoa-X in 2023.

Chips & compute

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AMD’s Venice-X maxes out family at 5.3 GHz, returning 3D V-Cache to data center after four years

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