The name is the button.

An agent writes the code now, and a human thumb hovers over Accept all a hundred times a day. The honest question of this decade is what, exactly, you just accepted. So I read the diff.

Eight years as a backend engineer in Stockholm, back in Tokyo since 2023, and I still ship something small most nights, usually badly. My one rule: the only real review of a model is the thing you built with it. That is why there is no leaderboard on this site.

Around a hundred and forty sources come through — the labs' own posts, the papers, the tools, the runtimes and languages nobody is watching yet, the chip under the demo, and the newsletters people actually forward. What is moving gets counted so the week reads at a glance, and every few days I explain one mechanism in plain words.

A story here is a headline, a short excerpt, one image and the link to whoever wrote it. We never reproduce the post; the images belong to their authors. A post written in Japanese appears in Japanese, exactly as it was published, and the link goes to the original.

— Yuki Halvorsen, Tokyo

← Accept All Archive

SemiEngineeringSilicon

Bringing Down Test Costs For Co-Packaged Optics

10.26

Key Takeaways: For FA, engineers need to identify boundaries and be able to decouple individual components to identify the root cause of problems.

Read at SemiEngineering ↗

One letter a week, starting soon.

Latest

Bringing Down Test Costs For Co-Packaged Optics

More from SemiEngineering on Accept All

SiliconSelf-Heating And Parasitics Challenge Multi-Tier CFET Scaling (TU Munich, IIT Kanpur) SemiEngineering

SiliconPt-W Alloy Shows Potential For Thinner High-NA EUV Mask Absorbers (Chinese Academy of Sciences et al.) SemiEngineering

SiliconDry-Deposited Resist Shows Different Tone Behavior Under EUV And E-Beam Exposure (KU Leuven, Kunsan, VUB, Imec) SemiEngineering

SiliconSilicon Photonic Modulator Reaches 200 Gb/s PAM4 With Reduced DSP (Science Tokyo, Yokohama, AIST, PETRA) SemiEngineering

SiliconSecurity-Aware Layer Mapping Reduces Fault Vulnerability In 3D Compute-In-Memory (ASU, U. of Maryland) SemiEngineering

SiliconNeural Networks Speed 3nm Nanosheet SPICE Simulation (TU Munich) SemiEngineering