The name is the button.

An agent writes the code now, and a human thumb hovers over Accept all a hundred times a day. The honest question of this decade is what, exactly, you just accepted. So I read the diff.

Eight years as a backend engineer in Stockholm, back in Tokyo since 2023, and I still ship something small most nights, usually badly. My one rule: the only real review of a model is the thing you built with it. That is why there is no leaderboard on this site.

Around a hundred and forty sources come through — the labs' own posts, the papers, the tools, the runtimes and languages nobody is watching yet, the chip under the demo, and the newsletters people actually forward. What is moving gets counted so the week reads at a glance, and every few days I explain one mechanism in plain words.

A story here is a headline, a short excerpt, one image and the link to whoever wrote it. We never reproduce the post; the images belong to their authors. A post written in Japanese appears in Japanese, exactly as it was published, and the link goes to the original.

— Yuki Halvorsen, Tokyo

← Accept All Archive

SemiEngineeringSilicon

E-Series GPU IP: The First Step Towards Converged Acceleration

September 30

E-Series, announced in 2025 and with first silicon expected by the end of 2026, marks a new era for edge system design.

Chips & compute

Read at SemiEngineering ↗

One letter a week, in your inbox.

Latest

E-Series GPU IP: The First Step Towards Converged Acceleration

Related

SiliconMake Your Interface Work For Your AI SoC—A 10 Step Program: IP Solutions And Models SemiEngineering

SiliconPCIe 8.0 Over UCIe 3.0: Bringing A Proven Protocol Into The Chiplet Era SemiEngineering

SiliconData Center Energy Trends Force A Rethink Of Chip Power Delivery SemiEngineering

SiliconPhotonics Fundamentals For Electronics Engineers: eBook SemiEngineering

SiliconTSMC OIP: Chip Industry Growth Blows Past Forecast SemiEngineering

AsiaChina’s DeepSeek open-sources tools to help Huawei chips supplant Nvidia in AI SCMP Tech