The name is the button.

An agent writes the code now, and a human thumb hovers over Accept all a hundred times a day. The honest question of this decade is what, exactly, you just accepted. So I read the diff.

Eight years as a backend engineer in Stockholm, back in Tokyo since 2023, and I still ship something small most nights, usually badly. My one rule: the only real review of a model is the thing you built with it. That is why there is no leaderboard on this site.

Around a hundred and forty sources come through — the labs' own posts, the papers, the tools, the runtimes and languages nobody is watching yet, the chip under the demo, and the newsletters people actually forward. What is moving gets counted so the week reads at a glance, and every few days I explain one mechanism in plain words.

A story here is a headline, a short excerpt, one image and the link to whoever wrote it. We never reproduce the post; the images belong to their authors. A post written in Japanese appears in Japanese, exactly as it was published, and the link goes to the original.

— Yuki Halvorsen, Tokyo

← Accept All Archive

EE TimesSilicon

Everspin Expands MRAM Push into AI Servers, Data Centers, Satellite Systems

10.22

Everspin Technologies is looking to expand its magnetoresistive random-access memory (MRAM) beyond established industrial applications into AI servers, data centers, and satellite systems, as AI…

Chips & compute

Read at EE Times ↗

One letter a week, starting soon.

Latest

Everspin Expands MRAM Push into AI Servers, Data Centers, Satellite Systems

Related

SiliconIndia’s OSAT Buildout Puts Semiconductor Testing in Focus EE Times

SiliconWhy Chip Design AI Benchmarks Must Go Beyond Functional Correctness EE Times

SiliconEdge AI MCU Features Multimodal Compute, Tiered Memory EE Times

SiliconHow Singapore Connects Chip Research, Startups, and Manufacturing EE Times

JapanAIに画面操作を任せる前に：computer useを安全に始める手順 Zenn (AI)

AsiaBAAI's FlagOS 2.2 Expands Its Cross-Chip Operator Libraries to 1,454 Operators Pandaily